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A circuit-level simulation model of PNPN devices

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2 Author(s)
Brambilla, A. ; Dept. of Electr. Eng., Pavia Univ., Italy ; Dallago, E.

A numerical model of a three-junction device is presented. It allows the simulation of the external characteristics of the PNPN family devices, and in this work the simulation of the gate turn-off thyristor is particularly considered. The reasons that led to the realization of this model are explained by reviewing previous works in this area. The model is based on the Ebers-Moll equations extended to include the three-junction devices, and it is implemented (built-up) in the source code of the SPICE2 circuit simulator. A detailed description of the implementation of the model equations and different tests are reported and discussed. The results are in accordance with the measurements from the devices reported on data sheets and the computation time is sufficiently short

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 12 )