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Long and short covering edges in combination logic circuits

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3 Author(s)
Wing-Ning Li ; Dept. of Comput. Sci., Arkansas Univ., Fayetteville, AR, USA ; Reddy, S.M. ; Sahni, S.

The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 12 )