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This paper proposes a 128-channel column-parallel two-stage time-to-digital converter (TDC) utilizing a time difference amplifier (TDA) and shows measurement results obtained from an implementation in a 0.35- μm CMOS process. The first stage operates as a coarse TDC, the time residue is amplified by a TDA, then converted by the second-stage TDC. As the gain of the time difference amplifier can be adjusted from 8.5 to 20.4, the time resolution of the TDC can be tuned from 21.4 to 8.9 ps. The time resolution variation due to process-voltage-temperature (PVT) effects is ± 5.8% without calibration when the time resolution is 12.9 ps. We propose a calibration method to compensate LSB changes due to the power supply fluctuation and temperature variation.