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Low-Power CMOS Super-Regenerative Receiver With a Digitally Self-Quenching Loop

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4 Author(s)
Kihyun Kim ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Sumin Yun ; Sungho Lee ; Sangwook Nam

A 500 MHz super-regenerative receiver (SRR) with a digitally self-quenching loop (DSQL) is designed for low-power/high-data-rate applications. The DSQL replaces the envelope detector used in a conventional SRR and minimizes the overall power consumption by generating a self-quench signal digitally for a super-regenerative oscillator. The receiver is fabricated using a 0.13 μm CMOS process. The chip size is 0.7 mm2 and the minimum energy usage is 0.09 nJ/b with a supply voltage of 1 V at a data rate of 10 Mbps. The measured sensitivity is - 76 dBm.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:22 ,  Issue: 9 )