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Wear-out simulation environment for VLSI designs

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2 Author(s)
Choi, G.S. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Iyer, R.K.

A simulation-based approach for the reliability prediction of VLSI designs is introduced. The approach combines the switch-level circuit simulation and the device-level Monte Carlo simulation to achieve a realistic reliability assessment. The Monte Carlo analysis makes use of importance sampling to reduce the run lengths. Key advantages of this approach are that it can closely mimic dynamic sequences of events in a device over time, localize the weak locations/aspects of a target chip, and generate time-to-failure (TIF) distribution for an entire VLSI chip. In the current implementation, two common IC failure modes (electromigration and oxide breakdown) are simultaneously simulated under varying operating environments and fabrication technology parameters. In particular, operating voltage, temperature, and the device dimension are varied, and the impact of technology improvements, such as reduced dimension, on reliability is quantified. The use of this environment for developing reliable VLSI systems is illustrated with a case study of a custom-designed microprocessor chip.

Published in:

Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on

Date of Conference:

22-24 June 1993