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A design technique for performing low-power decision-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-critical node within the feedback loop of the equaliser. Based on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power efficiency of the proposed architecture is analysed and is compared with that of conventional analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a proof-of-concept chip fabricated in 65 nm CMOS.