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Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a reference inverter using single-finger gate structure. On the other hand, doubling gate-pitch in the above inverter improves the pull-down and pull-up delay by ~ 18% and ~ 23%, respectively, compared with the delay of the reference inverter. In this brief, we present a methodology of transistor sizing and layout optimization for MFGSs in stress-engineered CMOS circuits. For this, we derive and validate a modified model of logical effort (LE), where LE is expressed as a function of the number of fingers (NF) and gate-pitch (Lpp). Using our model, we reduce the error in the estimated delay of a four-stage buffer with FO4 from ~ 9% to ~ 1%. Using our methodology, we improve the circuit performance by 7%.
Date of Publication: Nov. 2012