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High performance prime field multiplication for GPU

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3 Author(s)
Leboeuf, K. ; Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada ; Muscedere, R. ; Ahmadi, M.

This paper presents a high performance algorithm for modular multiplication on a graphics processing unit (GPU) implemented in assembler. The proposed algorithm carries out finite field multiplication over the NIST prime fields of size 192, 224, 256 and 384 bits. Included is a detailed explanation of our algorithm, an instruction count analysis, and a comparison to recently published work; compared to the next fastest design, the proposed algorithm's execution time is 27 to 71 times faster.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012

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