Skip to Main Content
A mismatch-tolerant current-mode Sigma Delta (ΣΔ) Digital to Analog Converter (DAC) is presented here. The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range even as the ΣΔ step size and range are kept small to minimize ΣΔ switching noise. Mismatch between DAC current elements can result in Differential Non Linearity (DNL) at the DAC output. A novel scheme is proposed to mitigate this effect. It involves skewing the thresholds of the quantizer in the ΣΔ modulator based on the DAC input, in order to control which DAC elements are used in generating a particular output current. The DAC, implemented as part of a Digital PLL in 90nm CMOS, yields a current range of up to 2mA and occupies an area of 0.035mm2. It is shown that the proposed scheme attenuates mismatch effects by a factor of 16.