Skip to Main Content
A low power, low complexity full adder design based on degenerate pass transistor logic (PTL) is described. The design kernel is a logically degenerate 5-transistor XOR-XNOR module supporting complementary outputs. In spite of the logic deficiency, this module functions properly in the context of full adder applications. The threshold loss problem common in most PTL designs can be alleviated due to the availability of complementary control signals. Combining this module with multiplexing modules, a novel full adder design using as few as 10 transistors us derived. The proposed full adder design features the least output signal degradation and the smallest Vdd operations against other 10-T counterpart designs. The performance edges in speed, power and power-delay product are also proved via post layout simulations.