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Substrate noise suppression technique for power integrity of TSV 3D integration

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3 Author(s)
Po-Jen Yang ; Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Po-Tsang Huang ; Wei Hwang

In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012