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A 0.02 nJ self-calibrated 65nm CMOS delay line temperature sensor

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2 Author(s)
Shuang Xie ; Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Wai Tung Ng

This paper presents an area and power efficient delay line based temperature sensor for on-chip monitoring. This sensor can be deployed in large numbers on a microprocessor chip to facilitate advanced thermal and power management techniques. The proposed self-calibration design eliminates the effort associated with two-point calibration commonly found in conventional temperature sensors. In addition, it saves digital decoding power by the use of both tab and counter decoding. Measurement results for a 65nm CMOS design show that the proposed temperature sensor consumes 0.02 nJ energy per conversion. It occupies an active area of 0.002 mm2 and has a resolution of 0.5°C with errors within ±2.0°C over a temperature range from 20 to 80°C.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012