A pre-emphasis circuit design for high speed on-chip global interconnect

On-chip global interconnects are speed and power bottleneck in state-of-the-art chips. Pre-emphasis technique is an efficient way to improve the performance of the global communication. This paper first performs delay analysis of a global wire to work with a pre-emphasis circuit in time domain. Based on the analysis, a new pre-emphasis circuit design is proposed. Simulation results show that the pre-emphasis circuit can increase the link bandwidth by more than 40% and 20% in capacitive and capacitive-resistive coupled 10mm global link respectively. The new pre-emphasis circuit design can be applied in high speed global communication.