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Multiple-input multiple-output (MIMO) technique can significantly increase data throughput without sacrificing additional bandwidth. However, data detection at the receiver and its VLSI implementation is challenge due to high computation complexity. This paper presents the VLSI architecture and implementation for a 4×4 64-QAM soft-output K-Best MIMO detector. A novel deeply pipelined architecture which makes use of all the full-length ZF-augmented discarded paths (DPs) is designed to reduce complexity and improve BER performance. Furthermore, to save area and latency, two improvement methods-abandoning DPs of bottom levels and performing ZF-augmentation at the last stage are proposed. The presented detector improves the BER performance by 2.3dB at BER=10-3 compared to the conventional soft K-Best scheme when using the minimum mean squared error-sorted QR decomposition (MMSE-SQRD). It can achieve a peak throughput of 855 Mbps while consuming 223K gates, 301pJ/bit and 102 cycles for latency in SMIC 0.13μm CMOS process.