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A low power hearing aid computing platform using lightweight processing elements

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4 Author(s)
Kuo-Chiang Chang ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Yu-Wen Chen ; Yu-Ting Kuo ; Chih-Wei Liu

This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012