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A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS

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4 Author(s)
Yu Lin ; Mixed-signal Microelectron. Group, Eindhoven Univ. of Technol., Eindhoven, Netherlands ; Doris, K. ; Hegt, H. ; van Roermund, A.

This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (VT≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012

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