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This paper presents a CMOS RF receiver front-end suitable for ultra-low-power operation. In order to achieve desired gain and linearity of receiver front-end at a 1V supply voltage, current reuse and optimum gate biasing techniques are employed. The proposed architecture includes merged LNA and mixer, operating in the sub-threshold region, and designed for the 902-928MHz ISM band. The proposed circuit is designed in a 90nm CMOS Process and occupies 0.04mm2. The post-layout simulations of front end show a voltage gain of 17.8dB, a noise figure of 6.7 dB and IIP3 better than -8 dBm. Its power consumption is only 218uW from a 1V supply.
Date of Conference: 20-23 May 2012