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The main drawback of current-mode interface circuits for on-chip capacitive sensors is that the measurement sensitivity is adversely affected by the sensor parasitic capacitance. This causes a strong limitation in the range of applicability of CM interfaces. In this paper we propose a technique that avoids this problem and allows the design of high-performance CMOS interfaces. The proposed solution is based on a feedback loop that, during an autotuning phase, sets the driving current level, hence ensuring virtually the same accuracy irrespectively of the parasitic capacitance. The technique was implemented and designed using a 65-nm CMOS technology. Simulation results are found in close agreement with those theoretically expected, resulting also in an increased accuracy of the capacitive variation detection.
Date of Conference: 20-23 May 2012