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Fast parasitic-aware synthesis methodology for high-performance analog circuits

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2 Author(s)
Ahmed, A.A.I. ; Dept. of ECE, Memorial Univ. of Newfoundland, St. John''s, NL, Canada ; Lihong Zhang

In this paper a fast parasitic-aware synthesis approach of CMOS analog circuit is presented. Instead of the conventional approach of circuit sizing followed by layout generation, extraction and verification, we propose a method that considers the performance constraints and layout induced parasitics simultaneously within a concurrent phase of circuit synthesis. The proposed methodology is tested with high-performance analog circuits in different technologies and the experimental results demonstrate the high efficacy of this synthesis approach.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012