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Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

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12 Author(s)
Li-Wei Chu ; Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Chun-Yu Lin ; Shiang-Yu Tsai ; Ming-Dou Ker
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Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012

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