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Settling time and noise optimization of a three-stage operational transconductance amplifier

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2 Author(s)
Seth, S. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Murmann, B.

This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) in 90-nm CMOS that is used in a switched-capacitor (SC) gain stage clocked at 200 MHz. Existing design methods for three-stage OTAs lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal design with the best total integrated noise and settling time has been cohesively solved by formulating a nonlinear constrained optimization program. Equality, inequality, and semi-infinite constraints are formed using closed form symbolic expressions obtained by a closed loop analysis of the SC gain stage and the optimization program is solved by using the interior-point algorithm. Simulation results show that the amplifier achieves a ± 0.1% dynamic error settling time of 2.5 ns with a total integrated noise of 240 μVrms, while consuming 5.2 mW from a 1-V power supply.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012