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New FPN correction method for PD-storage dual-capture CMOS image sensor using a nonfully depleted pinned photodiode

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3 Author(s)
Lee, Jiwon ; Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea ; Baek, Inkyu ; Yang, Kyounghoon

This paper proposes a novel fixed pattern noise (FPN) reduction technique for a PD-storage dual-capture image sensor based on the 4-tansistor pixel structure. The knee-point calibration method using a nonfully depleted photodiode by controlling the transfer voltage is proposed, without any modification of the pixel structure or addition of circuit components. The prototype sensor is fabricated using a 0.13 µm CIS process. The chip includes a 320 × 240 pixel array with a 2.25 µm pixel pitch. The measurement results show that the proposed technique successfully reduces the FPN by 66% while preserving the inherent performance advantages of the PD-storage dual-capture CMOS image sensor.

Published in:

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference:

20-23 May 2012