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This paper proposes a novel fixed pattern noise (FPN) reduction technique for a PD-storage dual-capture image sensor based on the 4-tansistor pixel structure. The knee-point calibration method using a nonfully depleted photodiode by controlling the transfer voltage is proposed, without any modification of the pixel structure or addition of circuit components. The prototype sensor is fabricated using a 0.13 µm CIS process. The chip includes a 320 × 240 pixel array with a 2.25 µm pixel pitch. The measurement results show that the proposed technique successfully reduces the FPN by 66% while preserving the inherent performance advantages of the PD-storage dual-capture CMOS image sensor.