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A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture

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2 Author(s)
Zhu, Hongbo ; VLSI Design and Education Center (VDEC), The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan ; Shibata, T.

A VLSI image processor capable of extracting motion features from moving images in real time has been developed employing row-parallel and pixel-parallel architectures based on the digital pixel sensor (DPS) technology. Directional edge filtering of input images is carried out in row-parallel processing to minimize the chip real estate. To achieve a real-time response of the system, a fully pixel-parallel architecture has been explored in adaptive binarization of filtered images for essential feature extraction as well as in their temporal integration and derivative operations. As a result, self-speed-adaptive motion-feature-extraction has been established. The chip was designed and fabricated in a 65-nm CMOS technology and used to build an object detection system. Motion-sensitive target image localization was demonstrated as an illustrative example.

Published in:
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Date of Conference: 20-23 May 2012

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