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A Parallel Simulated Annealing Approach for the Mapping of Large Process Networks

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2 Author(s)
Galea, F. ; Embedded Real Time Syst. Lab., CEA, Gif-sur-Yvette, France ; Sirdey, R.

We propose a parallel simulated annealing approach to solve a dataflow process network mapping problem, where a network of communicating tasks is mapped into a set of processors with limited resource capacities, while minimizing the overall communication bandwidth between processors. The speedups obtained using this approach enables us to solve problems with more than one thousand tasks, on up to 48 processors, in reasonable time. Results have been obtained by taking profit of the specific architecture of a Non-Uniform Memory Access (NUMA) computer.

Published in:

Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International

Date of Conference:

21-25 May 2012