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Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier

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2 Author(s)
Kumar Jaiswal, M. ; Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong, China ; Cheung, R.C.C.

Floating point multiplication is a crucial and useful arithmetic operation for many scientific and signal processing applications. High precision requirements of many applications lead to the incorporation of quadruple precision (QP) arithmetics. The logic complexity and performance overhead of quadruple precision arithmetic are quite large. This paper has focused on one of the quadruple precision arithmetic operations, multiplication. We present an efficient implementation of QP multiplication operation on a reconfigurable FPGA platform. The presented design uses much less hardware resource in terms of DSP48 blocks, and slices with a higher performance. Promising results are obtained by comparing the proposed designs with the best reported QP floating point multiplier in the literature. We have achieved more than 50% improvements in the amount of DSP48 block at a slight cost of additional slices, on a Virtex-4 FPGA.

Published in:

Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International

Date of Conference:

21-25 May 2012