Skip to Main Content
A multistage shift register using the parallel connection technique of n-channel nanowire transistors for low output noise is proposed. The proposed circuit decreases the output noise by eliminating the direct connection of the clock signal to the gate of the pull-down transistor of the output stage. Measured results show that the output noise of the proposed circuit is under 0.16 V when the input voltage is 5.0 V and the operating frequency of the proposed circuit is 900 Hz at the capacitive load of 150 pF. The maximum operating frequency of the proposed circuit at the loading condition of the wide-video-graphic-array resolution can be up to 46 kHz.