By Topic

Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ghosh, J. ; Dept. of Electr. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India ; Mukhopadhyay, S. ; Patra, A. ; Culpepper, B.
more authors

This paper presents a technique to study and estimate the dc performance of lateral power MOSFET switches used in on-chip dc-dc converters. The dc performance is characterized by the on-resistance and current distribution profile in the switch layout. In the proposed approach, a netlist is generated that consists of the parasitic resistances extracted from the metal interconnects along with the MOS device fingers present in the layout. This approach is modular and exploits repetitive patterns of power MOSFET layouts to expedite the extraction process. The extracted resistance values are computed from the geometrical and technological parameters of the metal polygons without the requirement of solving complex electromagnetic (EM) field equations. Comparison of results with an industry standard EM solver tool as well as experimental measurements amply demonstrates the computational efficiency and accuracy of the approach.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:31 ,  Issue: 9 )