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A stacked Si3N4/HfO2 charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si3N4 to Si and the higher barrier for electron detrapping from HfO2 to Si3N4. The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al2O3 between Si3N4 and HfO2 as the CT layer. This is because most of the injecting charges are trapped at the Si3N4/Al2O3 interface, and Al2O3 also provides a high barrier for electron detrapping.