By Topic

Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With \hbox {Si}_{3}\hbox {N}_{4}/\hbox {Al}_{2}\hbox {O}_{3}/\hbox {HfO}_{2} Charge-Trapping Layer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Zong-Hao Ye ; Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Kuei-Shu Chang-Liao ; Cheng-Yu Tsai ; Tzu-Ting Tsai
more authors

A stacked Si3N4/HfO2 charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si3N4 to Si and the higher barrier for electron detrapping from HfO2 to Si3N4. The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al2O3 between Si3N4 and HfO2 as the CT layer. This is because most of the injecting charges are trapped at the Si3N4/Al2O3 interface, and Al2O3 also provides a high barrier for electron detrapping.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 10 )