Cart (Loading....) | Create Account
Close category search window
 

The comparative analysis of the efficiency of regular and pseudo-optimal topologies of networks-on-chip based on Netmaker

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Romanov, O. ; Dept. of Design of Electron. Digital Equip., Nat. Tech. Univ. of Ukraine, Kiev, Ukraine ; Lysenko, O.

The different approaches to the optimization of network communication subsystem on a chip are considered. The regular and pseudo-optimal topologies with 9 nodes, using System Verilog library Netmaker are modeled. It is shown, that the pseudo-optimal topologies are highly efficient for the cases of network design with the number of nodes and connecting lines not achieved, when using typical regular topologies.

Published in:

Embedded Computing (MECO), 2012 Mediterranean Conference on

Date of Conference:

19-21 June 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.