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High speed with low power folding and interpolating ADC using two types of comparator in CMOS 0.18um technology

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5 Author(s)
Ahmad, W.R.W. ; Dept. of Electron., Univ. Teknol. MARA, Shah Alam, Malaysia ; Hassan, S.L.M. ; Halim, I.S.A. ; Abdullah, N.E.
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This paper describes the design of a 8-bit CMOS folding and interpolating Analog to Digital Converter (ADC) with high speed comparator. The objective of this paper is to design and identify the performance of the ADC with two types of comparator. Another objective of this paper is to minimize the power consumption of the ADC circuit from a comparator. Flash ADC is one of the faster ways to convert any analog signal to a digital signal. It uses folding and interpolating techniques allow each comparator of the ADC to be reused several times over the full scale input range. In addition, interpolating technique can reduce the number of folding circuit required in a folding ADC hence further improve the performance of the ADC in term of capacitive loading and power consumption. Besides that, 70 percent speed of the ADC also depends on the comparator. If we use very fast and stable comparator, the ADC will be more fast and effectively to do the next applications. The simulation results indicate that the comparator design 1 achieved lower power operation rather than comparator design 2 with a minimum number of transistors used, 2GHz of input signal and 497.02mW of power consumption from a single 2V supply based to Gateway Silvaco EDA tools simulation result.

Published in:

Humanities, Science and Engineering Research (SHUSER), 2012 IEEE Symposium on

Date of Conference:

24-27 June 2012