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Embedded Linux for concurrent dynamic partially reconfigurable FPGA systems

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4 Author(s)
Lesau, V.G. ; Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada ; Chen, E. ; Gruver, W.A. ; Sabaz, D.

Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that enables the development of embedded systems with hot swappable logic on the FPGA fabric. This means that hardware logic can be swapped in and out on-the-fly while the rest of the system is operational. Since DPR is relatively new, tool support is still evolving. This paper introduces new FPGA architectural tools and Linux OS modifications that aid in supporting DPR on FPGAs for control. We emphasize that control systems benefit from real hardware concurrency, meaning that by moving the control intelligence into hardware we minimize the negative effects inherent to threads and their scheduler. This leaves software with the role of a high-level administrator rather than an executor, thus eliminating unnecessary bottlenecks. The developed tools enable the hardware engineer to develop DPR-FPGA systems more effectively for rapid control system development.

Published in:

Adaptive Hardware and Systems (AHS), 2012 NASA/ESA Conference on

Date of Conference:

25-28 June 2012