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Test Path Selection for Capturing Delay Failures Under Statistical Timing Model

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4 Author(s)
Zijian He ; State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China ; Tao Lv ; Huawei Li ; Xiaowei Li

This paper proposes a test path selection approach for capturing delay failures caused by the accumulated distributed small delay variations. First, a universal path candidate set U, which contains testable long paths, is generated. Second, given a path number threshold, path selection from U is performed with the objective of maximizing the capability to capture potential delay failures. The path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that all the paths in a specified path set meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time efficient and achieves higher probability of capturing delay failures than traditional path selection approaches.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 7 )