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Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer

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2 Author(s)
Ting-Chi Tong ; Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Yun-Nan Chang

This paper presents a small and fast VLSI architecture of a vector graphics rasterization accelerator. To decide the filling regions of a graphics object, a large on-chip scan-line buffer (SB) is very often used and frequently accessed to derive the pixel's winding count. This paper, first, proposes a special 2-bit coding scheme for buffer entry along with active-edge-table rescan to record the intersection information of scan lines and the object paths. Second, for AA rendering applications, a coverage buffer is proposed to avoid the duplication of SBs. Compared with the conventional approach, the required buffer size can be reduced by up to 89%. Besides buffer reduction, this paper also proposes a hierarchical SB architecture in which the upper-level buffer indicates which scan-line sections have intersected with objects in order to skip the access to successive buffer entries. The same technique, along with the differential coverage transformation, can also be applied to coverage buffer. Our experimental results show that more than 87% of memory accesses can be reduced, which results in saving 66.4% of clock cycles in practical hardware implementation. The gate count of the proposed rasterization accelerator is only about 32 232, and can run at 250 MHz under UMC 90-nm technology for HDTV applications.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 7 )