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Wafer-level isotropic etching of silicon with XeF2 gas has been investigated for microelectromechanical-system (MEMS) fabrication. Because of the large exposed silicon area in the wafer-level process, XeF2 gas diffusion in the wafer-level process is different from the chip-level process. The silicon etch rate for the wafer-level XeF2 process is much smaller than chip-level XeF2 etching. Additionally, the silicon etch rate drops off as the etching time increased. The aperture size effect is apparent in the wafer-level XeF2 processing. However, for etching windows with a large size, the aperture size effect will be minimized. Both vertical and lateral aperture size effects depend on the number of etch cycle. Although slight anisotropy is also observed, wafer-level XeF2 etching shows a better isotropy than the chip-level process. Compared with the chip-level process, wafer-level XeF2 etching shows a large etch rate for SiO2. The etch selectivity between silicon and SiO2 is lower than 1000:1. Based on the characteristics of XeF2 etching, the layout design rule for the MEMS device with XeF2 releasing is developed and demonstrated.