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A bus-efficient low-latency network interface for the PDSS multicomputer

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4 Author(s)
Steele, S. ; USC Inf. Sci. Inst., Marina del Rey, CA, USA ; Draper, J. ; Koller, J. ; LaCour, C.

The Packaging-Driven Scalable Systems multicomputer (PDSS) project uses several innovative interconnect and routing techniques to construct a low-latency, high-bandwidth (1.3 GB/s) multicomputer network. The PDSS network interface provides a low-latency interface between the network and the processing nodes that allows unprivileged code to initiate network operations while maintaining a high level of protection. The interface design exploits processor-bus cache coherence protocols to deliver very-low-latency cache-to-cache communications between processing nodes. Network operations include a variety of transfers of cache-line-sized packets, including remote read and write, and a distributed barrier-synchronization mechanism. Despite performance-limiting flaws, the initial single-chip implementation of the network router and interface achieves gigabit/s bandwidth and microsecond cache-to-cache latencies between nodes using commodity processor and memory components

Published in:

High Performance Distributed Computing, 1997. Proceedings. The Sixth IEEE International Symposium on

Date of Conference:

5-8 Aug 1997

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