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Hardware realization of a Java virtual machine for high performance multimedia applications

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3 Author(s)
Berekovic, M. ; Lab. fur Informationstechnol., Hannover Univ., Germany ; Kloos, H. ; Pirsch, P.

This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The proposed architecture supports parallel execution of multiple Java threads. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip

Published in:

Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on

Date of Conference:

3-5 Nov 1997

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