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In the early stages of a chip design, i.e. before RTL coding is complete, before a cell library is selected, and before a package is selected, it can be beneficial to run some cost estimates on the silicon, package, and board to determine the feasibility of a project. The main questions to be answered in this are, “Can it be built in a reasonable amount of time, and how much will it cost to make and package a silicon die or dice?” This paper proposes a methodology to answer these questions. This methodology is especially useful in doing 2.5-D IC design and will be described in the context of a silicon interposer flow.