Skip to Main Content
This paper investigates the integration of Nanoelectromechanical (NEM) relays on top of TSVs, to reduce area overhead and also enable possible novel architecture design. NEM relay is used in this work to reduce the cost due to the removal of area overhead caused by TSV redundancy logic and the improvement of TSV reliability. Furthermore, novel memory architecture design with NEM relay is proposed to improve the cost efficiency by leveraging the switch made by NEM relay. The general-purpose memory can be reused in different designs, which allows the memory to be massively produced and thus amortizes the NRE cost. The experimental results show that the 3DIC chip can achieve 13.5% cost reduction with NEM relay integration.