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Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC

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4 Author(s)
Won-Myoung Ki ; University of Science & Technology, Electronic Packaging Engineering, 176, Daejeon, 305-333, Korea ; Myong-Suk Kang ; Sehoon Yoo ; Chang-Woo Lee

3D packaging technology has been studied actively due to requirement of high performance, high density, and multifunction on electronic devices. This study investigated formation and bonding process of ultra-fine Cu pillar bump on both sides of Si thin wafer for 3D IC. Thickness of the thin wafer was 100μm. The bumps for the interconnection were formed as Sn-3.5Ag cap bump on Cu pillar bump by electroplating method. The diameter and height of the bump were 20μm, respectively. Thin Si chip was joined at bonding load 1.5N and bonding temperature 260°C by flip-chip bonder and then reflow process was added for 15~20 seconds at 260°C. After reflow process, thickness of IMCs in the Sn/Cu pillar interface was nearly the same compared with only flip-chip bonding method. And the effect of self-alignment was found.

Published in:

3D Systems Integration Conference (3DIC), 2011 IEEE International

Date of Conference:

Jan. 31 2012-Feb. 2 2012