By Topic

Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Nakahira, K. ; Fracture & Reliability Res. Inst., Tohoku Univ., Sendai, Japan ; Endo, F. ; Furuya, R. ; Suzuki, K.
more authors

Since the residual stress in a silicon chip mounted in 3D modules causes the degradation of both electrical and mechanical reliability, the dominant factors of the residual stress was investigated by using a finite element method and experiments applying 2-μm long piezoresistance strain gauges. The residual stress and local deformation of the chip were found to vary drastically depending on the mechanical properties of bumps and underfill and bump alignment structures.

Published in:

3D Systems Integration Conference (3DIC), 2011 IEEE International

Date of Conference:

Jan. 31 2012-Feb. 2 2012