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This Paper presents on 3D stacking technology with 2.5μm × 2.5μm In (Indium) bump connections with adhesive injection . Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In order to minimize those effects, we have optimized the layout, process parameter and device structure.