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Design for high throughput SHA-1 hash function on FPGA

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3 Author(s)
Jae-woon Kim ; Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea ; Hu-ung Lee ; Youjip Won

In this paper, we propose SHA-1 architectures to achieve high-throughput hardware implementations. Two techniques such as loop unfolding and pre-processing were used for high-speed SHA-1 core design. The system is made of four sub-modules to increase throughput. Xilinx Virtex-6 FPGA is used for implementation. Implemented SHA-1 module achieves a throughput of 7.35 Gbps, and its behavior has been verified by connecting with Xilinx MicroBlaze soft processor.

Published in:

Ubiquitous and Future Networks (ICUFN), 2012 Fourth International Conference on

Date of Conference:

4-6 July 2012

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