Referenced Items are not available for this document.
In this paper, we propose SHA-1 architectures to achieve high-throughput hardware implementations. Two techniques such as loop unfolding and pre-processing were used for high-speed SHA-1 core design. The system is made of four sub-modules to increase throughput. Xilinx Virtex-6 FPGA is used for implementation. Implemented SHA-1 module achieves a throughput of 7.35 Gbps, and its behavior has been verified by connecting with Xilinx MicroBlaze soft processor.
Published in:
Ubiquitous and Future Networks (ICUFN), 2012 Fourth International Conference on
Date of Conference: 4-6 July 2012
- Page(s):
- 403 - 404
- ISSN :
- 2165-8528
- E-ISBN :
- 978-1-4673-1376-6
- Print ISBN:
- 978-1-4673-1377-3
- INSPEC Accession Number:
- 12932957
- Conference Location :
- Phuket
- Digital Object Identifier :
- 10.1109/ICUFN.2012.6261737
- Product Type:
- Conference Publications
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