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Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

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4 Author(s)
Kumari, V. ; Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India ; Saxena, M. ; Gupta, R.S. ; Gupta, M.

In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.

Published in:

Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 10 )

Date of Publication:

Oct. 2012

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