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A D-band CMOS power amplifier in 65-nm CMOS with wider than 30 GHz small signal gain bandwidth is developed by using proposed impedance transform network to split original matching network into 8-ways to integrate 8 transistors. Without using additional combining networks, the 4-stage power amplifier achieves 13.2 dBm saturation output power with 1.2 V supply at 140 GHz in a compact size of 0.38 mm2. The peak power-added efficiency is 14.6% with 115.2 mW dc power.
Date of Conference: 17-22 June 2012