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This paper presents the design of a low-voltage frequency synthesizer for Mode-1 MB-OFDM UWB applications. The proposed approach features a new system architecture and circuit implementation with reduced number of on-chip inductors, silicon area and power consumption. The synthesizer is fabricated in a 0.18-µm RF CMOS process, with the measured phase noise level of −119.4 dBc/Hz at 10 MHz offset from carrier (4.488 GHz) and sideband suppression of better than 43.7dBc. This chip occupies a core area of 1.2 × 0.35 mm2 and consumes 29.6 mW from a 1.2V power supply.
Date of Conference: 17-22 June 2012