The linearity and power added efficiency (PAE) of the power amplifier (PA) are improved by reversed body bias (RBB) using 0.18-µm CMOS technology and the bias dependence of the circuit performances is investigated. Negative bias to the bulk and forward bias to the deep n-well of the MOSFET devices are used to reduce the effects of the parasitic diodes and change the threshold voltage (Vth), leading to enhanced linearity and power added efficiency for the PA. The 24-GHz PA for demonstration is a two-stage design using cascode RF NMOS configuration with reverse body bias techniques have resulted in a maximum measured output power of 19 dBm, an OP1dB of 15.7 dBm, a PAE of 24.7%, and a linear gain of 19 dB when VDD and VDNW both biased at 3.6 V, and VBody biased at −3.6V. The chip size with all testing pads is only 0.56 × 0.67 mm2. To the author's knowledge, this is the first demonstration of the reversed body-bias applied to CMOS PAs and achieved significant improvement of PAE and OP1dB.