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New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High-Performance Imaging Sensor

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3 Author(s)
Xiangliang Jin ; Fac. of Mater., Optoelectron., & Phys., Xiangtan Univ., Xiangtan, China ; Zhibi Liu ; Jun Yang

This paper presents a high-performance complementary metal-oxide-semiconductor (CMOS) imager with a new analog-to-digital-converter (ADC) scheme. The new ADC scheme, adopting the visual perception of human eyes, has realized a maximal 13 bit variable resolution and reduced clipped noise for imaging. The response probability of human eyes to a flashlight falls in the region of [-1+σ, 1-σ] of a normal distribution, where σ is the standard deviation. In the region effective to human eyes [-1+σ, 1-σ], there exists a point corresponding to a maximum 13 bit variable resolution to improve the image quality and to save the power consumption and the chip size of sensors. The new ADC architecture uses an adjustable reference at both the top and bottom of the series of nonuniform resistors to reduce the clipped noise and to provide a wide dynamic range to image sensors. Based on reports of similar device design in the literature, this paper is particularly related to achieving a higher performance without increasing the chip size and power consumption. UXGA CMOS sensors with the newly developed ADC scheme are fabricated by the 0.18-μm CMOS process. The test results show improved image quality compared to typical CMOS products with a linear ADC. Test results also show 79-dB signal-to-noise ratio (at gain=0 dB) with a power consumption of 90 mW at 54 MHz.

Published in:

Sensors Journal, IEEE  (Volume:13 ,  Issue: 1 )