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Low-power architecture of dTDMA receiver and transmitter for hybrid SoC interconnect

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2 Author(s)
Khan, M.A. ; Centre for Dev. of Adv. Comput., Gov. of India, Noida, India ; Ansari, A.Q.

Performance of the buses is degraded by the increasing number of processing elements and transaction oriented model. This has attracted the attention for applying wireless network protocols like CDMA, TDMA, dTDMA etc in SoC. The TDMA systems use a static number of timeslots regardless of the number actual request allocated. This protocol wastes bandwidth when some timeslots are not allocated. In order to overcome this problem dynamic TDMA (dTDMA) has been proposed [5, 6]. The timeslot in dTDMA is managed by independently programmed fully-tapped feedback shift registers (FSR). Accordingly, if there are 2 allocated timeslots to processing element `A' and `D' then the FSR will load timeslot configuration data as {1000, 0100} respectively. The processing element `B' and processing element `C' have made no request so it will load the initial data as {0000}. The flip-flop of FSR at processing element `B' and `C' will do switching activity though no activity is required. In a similar way, at processing element `A' and `D', only two FSR need to be active since the number of slot is two only. But, all four flip-flops are active. A global gated-clock and shutdown logic is presented in which power consumption is reduced by deactivating the clock signal on both the FSR and at flip-flop level. The designed is synthesized using 0.35 micron TSMC Technology. The power consumption of the presented dTDMA circuit is 40% lower than that of a conventional dTDMA when the D-input has a reduced switching activity.

Published in:

Emerging Trends in Networks and Computer Communications (ETNCC), 2011 International Conference on

Date of Conference:

22-24 April 2011