By Topic

Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Houssany, S. ; EADS France the European Aeronautic Defense and Space Company, Innovation Works, Suresnes, France ; Guibbaud, N. ; Bougerol, A. ; Leveugle, R.
more authors

Static raw soft-error rates (SER) of COTS microprocessors are classically obtained with particle accelerators, but they are far larger than real application failure rates that depend on the dynamic application behavior and on the cache protection mechanisms. In this paper, we propose a new methodology to evaluate the real cache sensitivity for a given application, and to calculate a more accurate failure rate. This methodology is based on the monitoring of cache accesses, and requires a microprocessor simulator. It is applied in this paper to the LEON3 soft-core with several benchmarks. Results are validated by fault injections on one implementation of the processor running the same programs: the proposed tool predicted all errors with only a small over-estimation.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:59 ,  Issue: 4 )